Publications and Patents

Citation: 1000, H-index: 15 (Février 2019)

Books and Chapters (3)

  1.  French SKA White Book “The French community towards the Square Kilometre Array” Available at arXiv, Cornell University. ref. 1712.06950v1. December 2017. https://ska-france.oca.eu/images/SKA-France-Media/FWB_051017.pdf
  2. Maxime Pelcat, Slaheddine Aridhi, Jonathan Piat, J-F. Nezan. Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB. Springer. 224 pages. Août 2012. Review available : Martin, G. Let’s Get Physical. vol 31. IEEE Design Test. Number 4, issn 2168-2356, doi 10.1109. pp 60-61. Aug 2014.
  3. Pengcheng Mu, J-F. Nezan, Mickael Raulet. A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention”. Chapter in Lecture Notes in Electrical Engineering, Best papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009, Springer. Vol. 73, N°1, pp 217-236, Nov. 2010.

International journals (22)

  1.  Ahmed Kammoun, Wassim Hamidouche, Pierrick Philippe, Olivier Deforges, Fatma Belghith, Nouri Masmoudi, Jean-François Nezan. Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard. IEEE Transactions on Circuits and Systems for Video Technology, Institute of Electrical and Electronics Engineers, 2019
  2. Ahmed Kammoun, Wassim Hamidouche, Fatma Belghith, Jean-François Nezan, Nouri Masmoudi. Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard. IEEE Transactions on Consumer Electronics. pp 424-432. Volume 64, Issue 4. Nov. 2018
  3. Maxime Pelcat, Alexandre Mercat, Karol Desnos, Luca Maggiani, Yanzhou Liu, Julien Heulot, Jean-François Nezan, Wassim Hamidouche, Daniel Ménard, Shuvra S Bhattacharyya. Reproducible evaluation of system efficiency with a model of architecture: From theory to practice. EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol 37, Number 10. pp 2050-2063. 2018
  4. Zhang Jinglin, Zhiwei Liu, Jean-François Nezan. Correspondence matching among stereo images with object flow and minimum spanning tree aggregation. International Journal of Advanced Robotic Systems. Vol. 15, Number 2. 2018. 
  5. Judicael Menant, Guillaume Gautier, Muriel Pressigout, Luce Morin, Jean-François Nezan. An automatized method to parameterize embedded stereo matching algorithms. Journal of Systems Architecture Vol. 80, pp92-103. 2017
  6. Maxime Pelcat, Alexandre Mercat, Karol Desnos, Luca Maggiani, Yanzhou Liu, Julien Heulot, Jean-François Nezan, Wassim Hamidouche, Daniel Ménard, Shuvra S Bhattacharyya. Reproducible Evaluation of System Efficiency with a Model of Architecture: From Theory to Practice. TCAD, IEEE. 2017
  7. Karol Desnos, Maxime Pelcat, Slaheddine Aridhi, Jean-François Nezan. On Memory Reuse Between Inputs and Outputs of Dataflow Actors. ACM Transactions on Embedded Computing Systems (TECS). Vol 15, Number 2, pp1:25, DOI 10.1145/2871744. ISSN 1539-9087. May 2016.
  8. Karol Desnos, Maxime Pelcat, Jean-François Nezan, Slaheddine Aridhi. « Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs . Journal of Signal Processing Systems for Signal, Image, and Video Technology (JSPS). Springer Editions,pp1-19,DOI 10.1007/s11265-014-0952-6 September 2014.
  9. Zheng Zhou, William Plishker, Shuvra S.Bhattacharyya, Karol Desnos, Maxime Pelcat, Jean-François Nezan “Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing”, Journal of Signal Processing Systems
    for Signal, Image, and Video Technology (JSPS), Springer. October 2014.
  10. Manel Hentati, Samya Elaoud, Yassine Aoudni, Jean-François Nezan, Mohamed Abid, “An efficient Resource Management to Optimize the Placement of Hardware Task on FPGA in the RVC Framework”. Design Automation for Embedded Systems. DOI 10.1007/s10617-013-9115-4. Springer Science+Business Media. August 2013.
  11. Manel Hentati, Amor Nafkha, Pierre Leray, J-F. Nezan, Mohamed Abid. “Software Defined Radio Equipment: What’s the Best Design Approach to Reduce Power Consumption and Increase Reconfigurability?” International Journal of Computer Applications in Technology. pp26-32, Vol. 45, N° 14. doi 10.5120/6850-9417. May 2012.
  12. Matthieu Wipliez, Ghislain Roquier, J-F. Nezan. “Software Code Generation for the RVC-CAL Language”. Journal of Signal Processing Systems for Signal, Image, and Video Technology (JSPS),pages. pp203-213,vol.63,N°2, doi 10.1007/s11265-009-0390-z. May 2011
  13. Pengcheng Mu, J-F. Nezan, Mickael Raulet, J-G. Cousin. “Advanced list scheduling heuristic for task scheduling with communication contention for parallel embedded systems”. Journal Science China Information (SCI).  Vol 53, N°11, pp2272-2286. Nov 2010.
  14. Matthieu Wipliez, Ghislain Roquier, and Jean-François Nezan. Software code generation for the rvc-cal language. Springer Journal of Signal Processing Systems
    for Signal, Image, and Video Technology (JSPS), (Special Issue on Reconfigurable Video Coding: technologies, tools and methodologies for video codec reconfiguration), 2009.
  15. Fabrice Urban, Jean-François Nezan, and Mickael Raulet. HDS, a real-time multi-DSP motion estimator for mpeg-4 h.264 AVC high definition video encoding. Springer Journal of Real-Time Image Processing (JRTIP), 2009.
  16. Maxime Pelcat, Jonathan Piat, Matthieu Wipliez, Slaheddine Aridhi, and Jean-François Nezan. An open source rapid prototyping framework for signal processing applications. Eurasip Design and Architectures for Signal and Image Processing, (Special issue on Design and Architectures for Signal and Image Processing), 2009.
  17. Ihab Amer, Christophe Lucarz, Marco Mattavelli, Ghislain Roquier, Olivier Déforges, and Jean-François Nezan. Reconfigurable video coding: an overview of its main objectives. IEEE Signal processing Magazine, (Special Issue on Signal Processing on Platforms with Multiple Cores : Part 1 – Overview and Methodology), 2009.
  18. Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, and Olivier Déforges. A flexible heterogeneous Hardware/Software solution for Real-Time HD h.264 motion estimation. IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), pp 1781-1785, 2008.
  19. Markus Rupp, Thomas Kaiser, Jean-François Nezan, and Gerhard Schmidt. Signal processing with high complexity : Prototyping and industrial design. EURASIP Journal on Embedded Systems, 2 pages, 2006. Article ID 90363.
  20. Mickael Raulet, Fabrice Urban, Jean-François Nezan, Christophe Moy, Olivier Déforges, and Yves Sorel. Rapid prototyping for heterogeneous multicomponent systems: An MPEG-4 stream over a UMTS communication link. EURASIP Journal on Advances in Signal Processing, 13 pages, 2006. Article ID 64369.
  21. J.-F. Nezan, O. Déforges, M. Raulet : « Fast Prototyping Methodology for Distributed and Heterogeneous Architectures : Application to Mpeg-4 Video Tools ». Design Automation for Embedded Systems, Kluwer Academic Publishers. 2004
  22. V. Fresse, O. Deforges, J-F. Nezan. “AVSynDEx : a Rapid Prototyping process dedicated to the implementation of digital image processing applications on multi-DSP and FPGA architectures”. European Association for Signal, Speech and Image Processing (Eurasip) Journal on Applied Signal Processing, Implementation of DSP and Communication Systems Special Issue. Vol 2002, N°9, pp 990-1002.

International Conférences (69)

  1. Ahmed Kammoun, Wassim Hamidouche, Pierrick Philippe, Fatma Belghith, Nouri Masmoudi, Jean-François Nezan. Hardware Acceleration of Approximate Transform Module for the Versatile Video Coding Standard. Proceedings of the European Signal Processing Conference (EUSIPCO 2019). Coruna, Spain. Sept. 2019.
  2. Alexandre Honorat, Karol Desnos, Maxime Pelcat,  Jean-François Nezan. Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs. Proceedings of the 19th International Conference, SAMOS 2019. Samos, Greece, July 2019.
  3. Nicolas Sourbier, Jean-François Nezan, Cyril Tasse, Julien Hascoet. Optimization of Calibration Algorithms on a Manycore Embedded Platform. Proceedings of the 2018 IEEE Workshop on Signal Processing Systems (SIPS). Cape Town, South Africa. Oct. 2018.
  4. A. Kammoun, S. Ben Jdidia, F. Belghith, W. Hamidouche, Jean-François Nezan, N. Masmoudi. An optimized hardware implementation of 4-point adaptive multiple transform design for post-HEVC. In the proceedings of the IEEE 4th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP). March. 2018
  5. Julien Hascoet, Benoit Dupont de Dinechin, Karol Desnos, Jean-François Nezan. A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore. Proceeding of the IEEE High Performance Extreme Computing Conference (HPEC). Waltham, MA, USA. Sept. 2018
  6. Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin Martin, Benoit Dupont De Dinechin, Jean-François Nezan. Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. Proceeding of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM). pp 51-56. Manchester, United Kingdom. 2018.
  7. Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin Martin, Benoit Dupont De Dinechin, Jean-François Nezan. Demonstrating the SPIDER Runtime for Reconfigurable Dataflow Graphs Execution onto a DMA-based Manycore Processor. IEEE International Workshop on Signal Processing Systems. 2017
  8. Hamza Deroui, Karol Desnos, Jean-François Nezan, Alix Munier. Throughput Evaluation of DSP Applications based on Hierarchical Dataflow Models. Proceedings of the International Symposium on Circuits and Systemss (ISCAS) 2017
  9. Hamza Deroui, Karol Desnos, Jean-François Nezan Nezan, Alix Munier. Relaxed Subgraph Execution Model for the Throughput Evaluation of IBSDF Graphs. International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS). Samos, Greece, July 2017
  10. Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoit Dupont De Dinechin. Hierarchical Dataflow Model for efficient programming of clustered manycore processors. The 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2017
  11. Judicael Menant, Jean-François Nezan, Luce Morin, Muriel Pressigout. A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform. International Symposium on Electronic Imaging. Vol. 20, pp49-54. 2017
  12. Anas Jallouli, Fatma Belghith, Mohamed Ali Ben Ayed, Wassim Hamidouche, Jean-François Nezan. Statistical analysis of Post-HEVC encoded videos. Proceedings of the Signal Processing Systems (SiPS) IEEE International conference. 2017. 
  13. Jean-François Nezan, Alexandre Mercat, Patrice Delmas,Georgy Gimel’farb. Optimized Belief Propagation Algorithm onto Embedded Multi and Many-Core Systems for Stereo-Matching. Proceedings of the 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). Heraklion, Crete, Greece. 2016
  14. T. Gee, P. Delmas, S. Joly, V. Baron, R. Ababou, Jean-François Nezan. A dedicated lightweight binocular stereo system for real-time depth-map generation. Proceedings of the Design and Architectures for Signal and Image Processing (DASIP) conference. Rennes, France. 2016.
  15. Erwan Raffin, Erwan Nogues, Morgan Lacour, Maxime Pelcat, Daniel Menard, K. Desnos, Jean-Francois Nezan. Real-Time Low Power Software HEVC Decoder on Embedded GPP: A Side-by-Side Comparison. Design and Architectures for Signal and Image Processing (DASIP), Sep 2015, Cracow, Poland. 2015.
  16. Karol Desnos, Maxime Pelcat, and Jean-Francois Nezan, Slaheddine Aridhi. Buffer Merging Technique for Minimizing Memory Footprints of Synchronous Dataflow Specifications. Proceedings of the 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP). pp 1111-1115, Brisbane, Australia. April 2015.
  17. Julien Hascoet,  Jean-Francois Nezan, Andrew Ensor, Benoit Dupont de Dinechin. Implementation of a Fast Fourier Transform Algorithm onto a Manicure Processor. . Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). Cracow, Poland. September 2015.
  18. Julien Heulot, Maxime Pelcat, Jean-François Nezan, Yaset Oliva,  Slaheddine Aridhi, Shuvra Bhattacharyya. Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems. Proceedings of the 2nd IEEE Global Conference on Signal and Information Processing (GlobalSIP). December 3-5, 2014. Atlanta, Georgia, USA.
  19. Judicaël Menant, Muriel Pressigout, Luce Morin, Jean-François Nezan. «Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP». Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). Madrid, Spain. Oct 2014
  20. Julien Heulot, Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). Madrid, Spain. Oct 2014.
  21. Julien Heulot, Maxime Pelcat, Karol Desnos, Jean-François Nezan, Slaheddine Aridhi. « SPIDER: A Synchronous Parameterized and Interfaced Dataflow-Based RTOS for Multicore DSPs ». Proceedings of the 6th European Embedded Design in Education and Research (EDERC2014). Milan, Italy. September 2014
  22. Maxime Pelcat, Karol Desnos, Julien Heulot, Clément Guy, Jean-François Nezan, Slaheddine Aridhi. « PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming ». Proceedings of the 6th European Embedded Design in Education and Research (EDERC2014). Milan, Italy. September 2014.
  23. Alexandre Mercat, Jean-François Nezan, Daniel Menard Jinglin Zhang. «Implementation of a Stereo Matching algorithm onto a Manycore Embedded System ». Proceedings of the International Symposium on Circuits and Systemss (ISCAS) 2014. Pp 1296-1299. doi 10.1109/ISCAS.2014.6865380. Melbourne, Victoria, Australia, June 1-5, 2014.
  24. Jinglin Zhang, J-F. Nezan, J-G. Cousin “Real-Time GPU-based Local Stereo Matching Method”. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP). Cagliari, Italy. Oct 2013
  25. Zheng Zhou, Karol Desnos, Maximer Pelcat, Jean-François Nezan, William Plishker and Shuvra S. Bhattacharyya. “Scheduling of Parallelized Synchronous Dataflow Actors” IEEE International Symposium on System-on-Chip 2013 (SoC 2013) Tampere, Finland, October 23-24, 2013.
  26. Karol Desnos, Maxime Pelcat, J-F. Nezan, Slaheddine. Aridhi. “Pre- and Post-Scheduling Memory Allocation Strategies on MPSoCs” 2013 Electronic System Level Synthesis Conference (ESLsyn). Austin, Texas, USA. May 2013
  27. Karol Desnos, Maxime Pelcat, J-F. Nezan, Shuvra S. Bhattacharyya, Slaheddine Aridhi. PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration. International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XIII). Samos, Greece, July 2013
  28. Julien Heulot, Maxime Pelcat, Jani Boutelier, J-F. Nezan, Slaheddine Aridhi. Applying the Adaptive Hybrid Flow-Shop Scheduling Method to Schedule a 3GPP LTE Physical Layer Algorithm onto Many-Core Digital Signal Processors. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). Torino, Italy. June 2013.
  29. Julien Heulot, Yaset Oliva, Maxime Pelcat, J-F. Nezan, J-C. Prévotet. “Dataflow-based Adaptive Multicore Execution on a Xilinx Zynq Platform” Proceedings of Design, Automation and test in Europe (DATE). Dresden, Allemagne. Mars 2013.
  30. Manel Hentati, Yassine Aoudni, J-F. Nezan, Mohamed Abid. “Exploiting Partially Reconfigurable FPGA for performance Adjustment in the RVC Framework”. Proceedings of the 7th IEEE International Design and test Symposium (IDT). Doha, Qatar. Dec 2012
  31. Jinglin Zhang, J-F. Nezan, J-G. Cousin, Erwan Raffin.”Implementation of Stereo Matching Using High Level Compiler for Parallel Computing Acceleration” Proceedings of the 27th Image and Vision Computing New Zealand (IVCNZ).Dunedin, Nouvelle-Zélande. Nov. 2012
  32. Julien Heulot, Karol Desnos, J-F. Nezan, Maxime Pelcat, Mickael Raulet, Hervé Yviquel, P.-L. Lagalaye, J-C. Le Lann. “An Experimental Toolchain Based on High-Level Dataflow Models of Computation for heterogeneous MPSoC”. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP).Karlsruhe,Allemagne. Oct 2012.
  33. Manel Hentati, Yassine Aoudni, J-F. Nezan, Mohamed Abid. “A Hierarchical Implementation of Hadamard Transform using RVC-CAL Dataflow Programming and Dynamic Partial Reconfiguration”. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP).Karlsruhe,Allemagne. Oct 2012.
  34. Fabrice Urban, Olivier Déforges, J-F. Nezan. “Optimization of the motion estimation for parallel embedded systems in the context of new video standards. Applications of Digital Image Processing. San Diego, USA. 15 pages. doi = 10.1117/12.939469. Aug 2012.
  35. Karol Desnos, Maxime Pelcat, J-F. Nezan, Slaheddine Aridhi. “Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph”. Proceedings 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XII). Samos, Greece. July 2012.
  36. Jinglin Zhang, J-F. Nezan, J-G. Cousin. “Implementation of Motion Estimation Based on heterogeneous Parallel Computing System With OpenCL. Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications (HPCC). Liverpool, UK. June 2012.
  37. Nicolas Siret, Matthieu Wipliez, J-F. Nezan, Francesca Palumbo, Luigi Raffo. “Multi-Purpose Systems: A Novel Dataflow-Based Generation and Mapping Strategy”. Proceedings of the 2012 IEEE International Symposium of Circuits and Systems. Corée, May 2012.
  38. Nicolas Siret, Matthieu Wipliez, J-F. Nezan, Francesca Palumbo. “Generation of Efficient High-Level Hardware Code from Dataflow Programs”. Proceedings of Design, Automation and test in Europe (DATE). Dresden, Allemagne. Mars 2012.
  39. Manel Hentati, Yassine Aoudni, J-F. Nezan, Mohamed Abid, Olivier Déforges. “FPGA Dynamic Reconfiguration using the RVC Technology: Inverse Quantization Case Study. Proceedings of the IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP). Tampere, Finlande. Nov 2011.
  40. Nicolas Siret, J-F. Nezan, Aimad Rhatay. “Design of a Processor Optimized for Syntax Parsing in Video Decoders”. Proceedings of the IEEE Conference on Design and  Architectures for Signal and Image Processing (DASIP). Tampere, Finlande. Nov 2011.
  41. Yaset Oliva, Maxime Pelcat, J-F. Nezan, J-C. Prévotet, Slaheddine Aridhi. “Building a RTOS for MPSoC Dataflow Programming”. SoC 2011 Proceedings. Finlande. Oct 2011.
  42. Manel Hentati, Amor Nafkha, Xun Zhang, Pierre Leray, J-F. Nezan, Mohamed Abid. “The Study of the impact of architecture design on cognitive radio”. Proceedings of the 8th International Multi-Conference on Systems, Signals and Devices (SSD), 2011. doi 10.1109/SSD.2011.5981424. Mars 2011
  43. Marcus Barkowsky, Médéric Blestel, Mathieu Carnec, Adlen Ksentini, Patrick Le Callet, Gérard Madec, Raoul Monnier, J-F. Nezan, Romuald Pepion, Yohann Pitrey, J-F. Travers, Mickael Raulet, Alain Untersee. “An Overview of the SVC4QoE project” Proceedings of the SVCVision workshop, in conjunction with ACM Mobimedia conference 2010. Lisbon, Portugal. 2010.
  44. Maxime Pelcat, J-F. Nezan, Slaheddine Aridhi. “Adaptive Multicore Scheduling for the LTE Uplink. NASA/ESA Conference on Adaptive Hardware and Systems (Ahs). Anaheim, USA. 2010.
  45. Nicolas Siret, Matthieu Wipliez, J-F. Nezan, Aimad Rhatay. “Hardware code generation from dataflow programs”. Conference on Design and Architectures for Signal and Image Processing (DASIP. pp113 -120. UK. 2010.
  46. Nicolas Siret, Ismael Sabry, J-F. Nezan, Mickael Raulet. “A codesign synthesis from an MPEG-4 decoder dataflow description”. Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp1995 -1998. ISBN: 978-1-4244-5309-2 doi = 10.1109/ISCAS.2010.5537107.Paris, France. 2010.
  47. Pengcheng Mu, Jean-François Nezan, Mickael Raulet, and Jean-Gabriel Cousin. A list scheduling heuristic with new node priorities and critical child technique for task scheduling with communication contention. In Eurasip, editor, Workshop on Design and Architectures for Signal and Image Processing (DASIP’09), Nice France, 2009.
  48. Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi, and Jean-François Nezan. Scalable compile-time scheduler for multi-core architectures. In IEEE, editor, Proceedings of Design, Automation and Test in Europe (DATE’09), Nice France, 2009.
  49. Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi, and Jean-François Nezan. A static scheduling framework for deploying applications on multicore architectures. In IASTED, editor, Proceedings of Parallel and Distributed Computing and Networks (PDCN’09), Innsbruck, Autriche, 2009.
  50. Maxime Pelcat, Jean-François Nezan, Jonathan Piat, Jerome Croizer, and Slaheddine Aridhi. A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems. In Eurasip, editor, Workshop on Design and Architectures for Signal and Image Processing (DASIP’09), Nice France, 2009.
  51. Maxime Pelcat, Slaheddine Aridhi, and Jean-François Nezan. Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm. In Workshop on Design and Architectures for Signal and Image Processing (DASIP’08), Bruxelles Belgium, 2008.
  52. Ghislain Roquier, Matthieu Wipliez, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Software synthesis of CAL actors for the MPEG reconfigurable video coding framework. In IEEE International Conference on Image Processing (ICIP’08), pages 1408-1411, San-Diego USA, oct. 2008.
  53. Matthieu Wipliez, Ghislain Roquier, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Code generation for the MPEG recon_gurable video coding framework : From CAL actions to c functions. In IEEE International Conference on Multimedia and Expo (ICME’08), pages 1049-1052, Hanover Germany, june 2008.
  54. Pengcheng Mu, Mickael Raulet, Jean-François Nezan, and Jean Gabriel Cousin. Automatic code generation for Multi-Microblaze system with SynDEx. In European Signal Processing Conference (Eusipco’07), pages 1644-1648, Poznan ; Poland, 2007.
  55. Sylvain Moreau, Slaheddine Aridhi, Mickael Raulet, and Jean-François Nezan. On modeling the RapidIO communication link using the AAA methodology. Workshop on Design and Architectures for Signal and Image Processing (DASIP’07), Grenoble France, 2007.
  56. Alain Maccari, Fabrice Urban, Mickael Raulet, and Jean-François Nezan. Automatic code generation for interconnected distributed RAM in the AAA methodology : H264 motion estimation case study. Workshop on Design and Architectures for Signal and Image Processing (DASIP’07), Grenoble France, 2007.
  57. Fabrice Urban, Ronan Poullaouec, Jean-François Nezan, and Olivier Déforges. H.264 fractional motion estimation re_nement : a real-Time and low complexity hardware solution for HD sequences. In European Signal Processing Conference (Eusipco’07), pages 836-840, Poznan, Poland France, 2007.
  58. Jean François Nezan, Olivier Déforges, Fabrice Urban, and Ronan Poullaouec. Real-time multi-DSP motion estimator for MPEG-4 AVC/H.264 high definition video encoding. In IEEE, editor, International Conference on Signals and Electronics Systems (ICSES’06), pages 305-308, 2006.
  59. Ghislain Roquier, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Using RTOS in the AAA methodology automatic executive generation. In European Signal Processing Conference (Eusipco’06), Genova Italia, september 2006.
  60. Fabrice Urban, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Automatic DSP cache memory management and fast prototyping for multiprocessor image applications. In European Signal Processing Conference (Eusipco’06), Florence Italia, 2006.
  61. Mickael Raulet, Fabrice Urban, Jean-Francois Nezan, Christophe Moy, and Olivier Deforges.Syndex executive kernels for fast development of applications over heterogeneous architectures. In European Signal Processing Conference (Eusipco’05), Antalaya Turkey, 2005.
  62. J.-F. Nezan, M. Raulet, O. Déforges : “Développement d’un codec vidéo Mpeg-4 temps-réel embarqués sur architectures distribuées“. 2nd International Symposium on Image/Video Communications over fixed and mobile networks (ISIVC’04), Brest. 2004
  63. M. Raulet, M. Babel, O. Déforges, J.F. Nezan, Y. Sorel. “Automatic Coarse-grain Partitioning And Automatic Code Generation For Heterogeneous Architectures. IEEE Workshop on Signal Processing Systems (SIPS’03). 2003
  64. N. Ventroux, J-F. Nezan, M. Raulet, O. Deforges. “Rapid prototyping for an optimized Mpeg-4 decoder implementation over a parallel heterogeneous architecture”. 28th International Conference on Acoustics, Speech, and Signal Processing (ICASSP’03), Honk-Hong. 2003
  65. J-F. Nezan, M. Raulet, O. Deforges. “Integration of Mpeg-4 video tools onto multi-DSP architectures using AVSynDEx fast prototyping methodology”. IEEE Workshop on Signal Processing Systems (SIPS’02), San Diego, USA. 2002.
  66. Y. Le Mener, M. Raulet, J-F. Nezan, A. Kountouris, C. Moy. “SynDEx Executive Kernel Development for DSPs TI C6X Applied To Real-Time and Embedded Multiprocessors Architectures”. European Signal Processing Conference (Eusipco’02), Toulouse, France. 2002.
  67. J-F. Nezan, O. Deforges, M. Raulet. “Rapid Prototyping Methodology For multi-DSP TI C6x Platforms Applied to an Mpeg-2 Coding Application”. ACM Symposium on Parallel Algorithms and Architectures (SPAA’02), Winnipeg, Manitoba, Canada. 2002.
  68. J-F. Nezan, V. Fresse, O. Deforges and M. Raulet.              “AVSynDEx Methodology For Fast Prototyping of Multi-C6X DSP Architectures”. International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’02), pages 207-212. Las Vegas, Nevada, USA. 2002.
  69. J-F. Nezan, V. Fresse, O. Deforges. “Fast prototyping of parallel architectures: an Mpeg-2 coding application”. International Conference On Imaging Science, Systems and Technology (CISST’01), Las Vegas, Nevada, USA. 2001.

Invited Internationales Conférences (3)

  1. Jean-François Nezan. Design Space Exploration in the context of SKA. Computing for SKA (C4SKA). Auckland, NZ. February 2016.
  2. Jean-François Nezan, Matthieu Wipliez, Ghislain Roquier, Mickael Raulet, and Olivier Déforges. Software synthesis from the CAL language. In Workshop on DataFlow Modeling for Embedded Systems Using the CAL Actor Language, Pise Italy, Mai 2008.
  3. Jean-François Nezan and Ghislain Roquier. Lar image codec onto a multiprocessor architecture. In IEEE Signal Processing Society, editor, “DSP Campus”, showcase of Universities during 28th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ’06), Mai 2006.

National Conférences with review process (7)

  1. Pengcheng Mu, Jean-Gabriel Cousin, Jean-François Nezan, and Michael Raulet. Heuristique statique améliorée d’ordonnancement de tâches : impact sur le tri des tâches et sur l’allocation de processeur. In Colloque GRETSI – Traitement du Signal et des Images, Dijon, septembre 2009.
  2. Ghislain Roquier, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Génération automatique de code distribué à l’aide de RTOS : application au codage d’images LAR. In France Telecom R&D, editor, COmpression et REpr_esentation des Signaux Audiovisuels (CORESA), France, oct. 2006.
  3. Fabrice Urban, Jean-François Nezan, Olivier Déforges, and Ronan Poullaouec. Estimateur de mouvement temps réel multi-DSP pour l’encodage vidéo MPEG-4 AVC/H.264 haute définition. In France Telecom R&D,COmpression et REpr_esentation des Signaux Audiovisuels (CORESA), France, oct. 2006.
  4. N. Ventroux, J-F. Nezan, M. Raulet, O. Deforges. “Prototypage rapide d’un décodeur Mpeg-4 optimisé sur architectures hétérogènes parallèles”. Gretsi’03, Paris, France. Sept 2003.
  5. J-F. Nezan, O. Deforges, M. Raulet. “Intégration d’un décodeur Mpeg-4 sur architecture multi-C6x ”. Journées Francophones sur l’adéquation algorithme architecture (JFAAA’02), Monastir, Tunisie. Déc. 2002
  6. M. Raulet, J-F. Nezan, O. Deforges. “Développement d’un noyau d’exécutif SynDEx pour DSP TI C6x appliqué aux architectures multiprocesseurs temps-réel et embarquées ”. Journées Francophones sur l’adéquation algorithme architecture (JFAAA’02), Monastir, Tunisie. Déc. 2002
  7. J-F. Nezan, O. Deforges, V. Fresse. “Intégration rapide de services vidéo Mpeg sur architectures Parallèles ”. Gretsi’01, Toulouse, France. Sept. 2001

1.1.6  Conf. sans comité de lecture/contributions MPEG (9)

  1. MPEG – M14650. Jean-François Nezan, Mickael Raulet, and Olivier Déforges.: Preesm in the rvc framework, July 2007.
  2. MPEG – M14463 : Maxime Pelcat, Médéric Blestel, Mickael Raulet, Jean-François Nezan, and Olivier Déforges. Evolutions of rvc so as to handle svc decoding, April 2007.
  3. MPEG – M14965. Maxime Pelcat, Mickael Raulet, Olivier Déforges, Médéric Blestel, and Jean-François Nezan. Implementing svc from rvc avc : description of the specific svc fus, November 2007.
  4. MPEG – M15167. Mickael Raulet, Ghislain Roquier, Matthieu Wipliez, Jean-François Nezan, and Olivier Déforges : Update of cal2c code generation, January 2008.
  5. MPEG – M14457. Ghislain Roquier, Maxime Pelcat, Mickael Raulet, Matthieu Wipliez, Jean-François Nezan, and Olivier Déforges : A scheme for implementing mpeg-4 sp codec in the rvc framework, April 2007.
  6. MPEG – M16145. Matthieu Wipliez, Mickael Raulet, and Jean-François Nezan : Proposed changes for rvc-cal annex a of iso-iec, February 2009.
  7. MPEG – M15382. Matthieu Wipliez, Mickael Raulet, Ghislain Roquier, Jean-François Nezan, and Olivier Déforges : A fast simulation of rvc mpeg4 sp decoder using cal2c code generation, April 2008.
  8. MPEG – M14981. Matthieu Wipliez, Ghislain Roquier, Mickael Raulet, Jean-François Nezan, Marco Mattavelli, and Ian Miller : Status of cal2c code generation, November 2007.
  9. J-F. Nezan. “Intégration de services vidéo Mpeg sur architectures parallèles”. Rencontre du Groupe Régional de Recherche en Micro-ondes (G2RM). Rennes, France. 2001

Patents (2)

  1. N°FR10/52542: Dispositif de traitement permettant d’extraire un ensemble de données d’un mot de données, circuit électronique et procédé d’extraction de données correspondants. Nicolas Siret, Jean-François Nezan, Mickael Raulet, Aimad Rhatay. Avril 2010.
  2. N°PF080070: Method and device for encoding video data in a scalable manner using a hierarchical motion estimator. Auteurs : Fabrice Urban, Jean-François Nezan, Mickael Raulet, Philippe Guillotel. 13 juin 2008.

 

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